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Abstract
During the Q4 2022 Earnings Call on January 26th, 2023, Intel announced the discontinuation of new development of Tofino Switch ASIC product line. At the same time, it was announced that Intel will continue the P4 development on server-side, such as SmartNICs with high-speed packet processing processors called IPUs (MountEvans ASIC), FPGA and DPDK/IPDK. In addition to Intel, other chip vendors such as NVIDIA (Mellanox) and AMD (Pensando) are also promoting SmartNICs by adding them to their product lines. Furthermore, applying P4 to software target, on server operating systems like Linux, such as eBPF/XDP and Linux TC (Traffic Control) getting more popular.
The acceleration of R&D on “server-side high-speed packet processing” area has been driven by the use of SmartNICs by Hyper Giants such as Google and Microsoft in their commercial services. SmartNICs with IPU/DPUs have been in use for several years, and examples of their use cases are being published. For example, a detailed paper was published in April this year on the use of AMD Pensando in Azure [1]. In addition, frameworks for leveraging SmartNICs for use beyond Hyper Giants are being released and communities promoting these frameworks are becoming more active.
In this session, I will share the current status of server-side high-speed packet processing by providing technical descriptions of IPU/DPUs and SmartNICs equipped with them, use cases, and the status of communities promoting activities.
At the end of the session, I would like to discuss with the audiences about “How can we ourselves take advantage of this technology?”, “What issues need to be resolved in order to take advantage of this technology?”, “What issues do we need to solve in order to make use of this technology?” etc.
[1] https://www.usenix.org/conference/nsdi23/presentation/bansal
Place
2F Convention Hall
Date
Day3 Friday, July 7th, 2023/14:45～15:30(45Minutes)
Presenter
Kentaro Ebisawa(Toyota Motor Corporation)
